1:4 clock fanout buffe r comlink? series cy2dl814 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07057 rev. *b revised june 20, 2005 features ? low-voltage operation ?v dd = 3.3v ? 1:4 fanout ? single-input configurable for ? lvds, lvpecl, or lvttl ? four differential pairs of lvds outputs ? drives 50- or 100-ohm load (selectable) ? low input capacitance ? 85 ps typical outp ut-to-output skew ? <4 ns typical propagation delay ? does not exceed bellcore 802.3 standards ? operation at ? 350 mhz ? 700 mbps ? industrial versions available ? packages available include tssop/soic description the cypress cy2 series of network circuits is produced using advanced 0.35-micron cmos technology, achieving the industry?s fastest logic. the cypress cy2dl814 fanout buffer features a single lvds-, lvpecl-, or lvttl-compatible input and four lvds output pairs. designed for data-communication clock management applica- tions, the fanout from a single input reduces loading on the input clock. the cy2dl814 is ideal for both level translations from single ended to lvds and/or for the di stribution of lvds-based clock signals. the cypress cy2dl814 has configurable input and output functions. the input can be selectable for lvpecl/lvttl or lvds signal s while the output driver?s support standard and high driv e lvds. drive either a 50-ohm or 100-ohm line with a single part number/device. block diagram pin configuration output in+ in- q1a q1b q2a q2b q4a q4b q3a q3b cntrl lvds / lvpecl / lvttl config en1 en2 lvds cy2dl814 16-pin tssop/soic en1 config cntrl vdd in+ in- en2 gnd q1a q1b q2a q2b q3a q3b q4a q4b 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 [+] feedback
comlink? series cy2dl814 document #: 38-07057 rev. *b page 2 of 8 maximum ratings [1, 2] storage temperature: ................................ ?65 c to + 150 c ambient temperature:................................... ?40 c to +85 c supply voltage to ground potential (inputs and v cc only)....................................... ?0.3v to 4.6v supply voltage to ground potential (outputs only) ........................................ ?0.3v to v dd + 0.3v dc input voltage ................................... ?0.3v to v dd + 0.3v dc output voltage................................. ?0.3v to v dd + 0.9v power dissipation........................................................ 0.75w notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is intended to be a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operation sections of this spe cification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing i s not required. pin description pin number pin name pin standard interface description 6,7 in+, in? configurable differential input pair or single line. lvpecl default. se e config below. 3 cntrl lvttl/lvcmos converts into a hi gh drive driver from a standard lvds. standard drive (logic = 0) b/high drive/bus (logic = 1) 2 config lvttl/lvcmos converts inputs (in + /in ? ), (en, en#) from the default lvpecl/lvds (logic = 0) to lvttl/lvcmos (logic = 1) 1,8 en1, en2 lvttl/lvcmos enable/disable logic. see table 1 below for details. 16,15,14,13 12,11,10,9 q1a, q1b, q2a, q2b, q3a, q3b, q4a, q4b ldvs differential outputs. 4v dd power positive supply voltage 5 g nd power ground table 1. en1 en2 function table?differential input mode enable logic input outputs en1 en2 in+ in? qna qnb hxhlhl hxlhlh xlhlhl xllhlh lhxxzz table 2. output drive control for standard and bus/b/high drive b cntrl pin 3 binary value drive std impedance output voltage value 0 standard 100 ohm v0 = voutput 50 ohm v = 1/2 * v0 1 high drive/bus/b 100 ohm v = 2 * v0 50 ohm v = v0 [+] feedback
comlink? series cy2dl814 document #: 38-07057 rev. *b page 3 of 8 table 3. input receiver configuratio n for differential or lvttl/lvcmos config pin 2 binary value input receiver family input receiver type 1 lvttl in lvcmos single-ended, non-inverting, inverting, void of bias resistors 0 lvds low-voltage differential signaling lvpecl low-voltage pseudo (posit ive) emitter coupled logic table 4. function control of the ttl input logic used to accept or invert the input signal lvttl/lvcmos input logic input condition input logic output logic q pins, q1a or q1 ground in? pin 7 in+ pin 6 input true v cc in? pin 7 in+ pin 6 input invert ground in+ pin 6 in? pin 7 input true v cc in+ pin 6 in? pin 7 input invert table 5. power supply characteristics parameter description test conditions min. typ. max. unit i ccd dynamic power supply current v dd = max. input toggling 50% duty cycle, outputs open 1.5 2.0 ma/mhz i c total power supply current v dd = max. input toggling 50% duty cycle, outputs open fl=100 mhz 90 100 ma table 6. d.c electrical charac teristics: 3.3v?lvds input parameter description cond itions min. typ. max. unit v id magnitude of differential input voltage 100 600 mv v ic common-mode of differential input voltage i v id i (min. and max.) i vid i /2 2.4?( i vid i /2) v v ih input high voltage guaranteed logic high level config/cntrl pins 2 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current v dd = max. v in = v dd 10 20 a i il input low current v dd = max. v in = v ss 10 20 a i i input high current v dd = max., v in = v dd (max.) 20 a table 7. d.c electrical charac teristics: 3.3v?lvpecl input parameter description conditions min. typ. max. unit v id differential input voltage p-p guaranteed logic high level 400 2600 mv v cm common-mode voltage 1.65 2.25 v i ih input high current v dd = max. v in = v dd 10 20 a i il input low current v dd = max. v in = v ss 10 20 a i i input high current v dd = max., v in = v dd (max.) 20 a [+] feedback
comlink? series cy2dl814 document #: 38-07057 rev. *b page 4 of 8 table 8. d.c electrical characteri stics: 3.3v?lvttl/lvcmos input parameter description conditions min. typ. max. unit v ih input high voltage guaranteed logic high level 2 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current v dd = max. v in = 2.7v 1 a i il input low current v dd = max. v in = 0.5v ?1 a i i input high current v dd = max., v in = v dd (max.) 20 a v ik clamp diode voltage v dd = min., iin = ?18 ma ?0.7 ?1.2 v v h input hysteresis 80 mv table 9. d.c electrical charac teristics: 3.3v?lvds output parameter description conditions min. typ. max. unit i v od i differential output voltage p-p v dd = 3.3v, v in = v ih , or v il rl = 100 ohm 0.25 ? 0.45 v voc(ss) steady-state common-mode output voltage ??226mv delta voc(ss) change in voc(ss) between logic states ?50 3 50 mv voc(pp) peak to peak common mode output voltage ??150mv i os output short circuit qa = 0v or qb = 0v ? ? ?20 ma voh output voltage high rl = 100 ohm ? ? 1475 mv vol output voltage low 925 ? ? mv table 10.ac parameters parameter description conditions min. typ. max. unit rise time pin control (pin 3) logic is ?false? defaulting to 100 ohm output drivers. differential 20% to 80% cl?10 pf rl and cl to g nd 3 cl = c intrinsic and c external rl = 100 ohm ? ? 1.4 ns fall time ??1.4ns rise time pin control (pin 3) logic is ?true? defaulting to 50 ohm output drivers. differential 20% to 80% cl?10 pf rl and cl to g nd 3 cl = c intrinsic and c external rl = 50 ohm output boost ? 350 600 ps fall time ? 350 600 ps table 11.ac switching characteristics @ 3.3 v (v dd = 3.3v 5%, temperat ure = ?40c to +85c) parameter description cond itions min. typ. max. unit in [+,-] to q[a,b] data and clock speed t plh propagation delay ? low to high v od = 100 mv 3 4 5 ns t phl propagation delay ? high to low 3 4 5 ns t pd propagation delay 3 4 5 ns in [1,2] to q[a,b] control speed t pe enable (en) to functional operation ? ? 6 ns t pd functional operation to disable ? ? 5 ns q[a,b] output skews t sk(0) output skew: skew between outputs of the same package (in phase) ? 0.085 0.2 ns t sk(p) pulse skew: skew between opp osite transitions of the same output (t phl ?t plh ) ?0.2? ns t sk(t) package skew: skew between outputs of different packages at the same power supply voltage, temper- ature and package type. same input signal level and output load. v id = 100 mv ? ? 1 ns [+] feedback
comlink? series cy2dl814 document #: 38-07057 rev. *b page 5 of 8 notes: 3. all input pulses are supplied by a frequency generator with the following characteristics: t r and t f 1 ns; pulse rerate = 50 mpps; pulse width = 10 0.2 ns. 4. rl= 50 ohm 1% zline = 50 ohm 6?. 5. cl includes instrumentation and fixt ure capacitanc e within 6 mm of the ut. 6. tpa and b are used for prop delay and rise/fall measurements. tpc is used for voc measurements only and is otherwise connecte d to v dd- 2 . table 12.high frequency parametrics parameter description co nditions min. typ. max. unit fmax maximum frequency v dd = 3.3v 50% duty cycle tw(50?50) standard load circuit. ??400mhz fmax(20) maximum frequency v dd = 3.3v 20% duty cycle tw(50?50) lvpecl input v in = v ih (max.)/v il (min.) v out = v oh (min.)/v ol (max.) (limit) ??200mhz tw minimum pulse v dd = 3.3v lvpecl input v in = v ih (max.)/v il (min.) f= 100 mhz v out = v oh (min.)/v ol (max.)(limit) 1 ? ? ns 80% 20% 0v differential v0y - v0z tr tf 1.4 v 1.0 v 1.4 v 1.0 v 0v differential 0v differential 1.2 v cm 1.2 v cm v1a v1b v0y v0z t plh t phl tpa tpc tpb 50 50 standard termination pulse generator a b 10pf figure 1. differential receiver to driver propagation delay and driver transition time [3, 4, 5, 6] 2.0v 1.6v v i(a) v i(b) next device vod voc tpa tpc tpb 50 50 standard termination pulse generator a b figure 2. test circuit and voltage definition s for the driver common-mode output voltage [3, 4, 5, 6] [+] feedback
comlink? series cy2dl814 document #: 38-07057 rev. *b page 6 of 8 0.0v 100% 80% 20% 0% tr tf 1.4v 1.0v v i(a) v i(b) tpa tpc tpb 50 50 standard termination pulse generator a b 10pf figure 3. test circuit and voltage definitions for the differential output signal [3, 4, 5, 6] 1 inconfig lvcmos / lvttl lvttl/lvcmos in p u t a in p u t b gnd figure 4. lvcmos/lvttl single-ended input value [7] in c o n fig lvpecl & lvds lvds/lvpecl 0 figure 5. lvpecl or lvds differential input value [8] ordering information part number package type product flow cy2dl814zi 16-pin tssop industrial, ?40c to 85c cy2dl814zit 16-pin tssop?tape and reel industrial, ?40c to 85c cy2dl814si 16-pin soic industrial, ?40c to 85c cy2dl814sit 16-pin soic?tape and reel industrial, ?40c to 85c cy2dl814zc 16-pin tssop commercial, 0c to 70 c cy2dl814zct 16-pin tssop?tape and reel commercial, 0c to 70 c cy2dl814sc 16-pin soic commercial, 0c to 70 c cy2dl814sct 16-pin soic?tape and reel commercial, 0c to 70 c lead-free cy2dl814zxi 16-pin tssop industrial, ?40c to 85c cy2dl814zxit 16-pin tssop?tape and reel industrial, ?40c to 85c cy2dl814sxi 16-pin soic industrial, ?40c to 85c cy2dl814sxit 16-pin soic?tape and reel industrial, ?40c to 85c CY2DL814ZXC 16-pin tssop commercial, 0c to 70 c CY2DL814ZXCt 16-pin tssop?tape and reel commercial, 0c to 70 c cy2dl814sxc 16-pin soic commercial, 0c to 70 c cy2dl814sxct 16-pin soic?tape and reel commercial, 0c to 70 c notes: 7. lvcmos/lvttl single ended input value. ground either input: w hen on the b side then non-inversion takes place. if a side is g rounded, the signal becomes the complement of the input on b side. see table 4 . 8. lvpecl or lvds differential input value. [+] feedback
comlink? series cy2dl814 document #: 38-07057 rev. *b page 7 of 8 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimensions comlink is a trademark of cypress semiconductor corporation. all product and company names mentioned in this document are the trademarks of their respective holders. pin 1 id 0~8 16 l ea d( 150 mil) soic 1 8 916 seating plane 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.386[9.804] 0.393[9.982] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] dimensions in inches[mm] min. max. 0.016[0.406] 0.010[0.254] x 45 0.004[0.102] reference jedec ms-012 part # s16.15 standard pkg. sz16.15 lead free pkg. package weight 0.15gms 16-lead (150-mil) soic s16.15 51-85068-*b 4.90[0.193] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 16 pin1id 6.50[0.256] seating plane 1 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] bsc. 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] bsc 0.25[0.010] 0-8 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] plane gauge dimensions in mm[inches] min. max. reference jedec mo-153 package weight 0.05 gms part # z16.173 standard pkg. zz16.173 lead free pkg. 16-lead tssop 4.40 mm body z16.173 51-85091-*a [+] feedback
comlink? series cy2dl814 document #: 38-07057 rev. *b page 8 of 8 document title: comlink? series cy2dl814 1:4 clock fanout buffer document number: 38-07057 rev. ecn no. issue date orig. of change description of change ** 115362 07/10/02 ehx new data sheet *a 122744 12/14/02 rbi added power up requirements to maximum ratings information. *b 384077 see ecn rgl added lead-free devices added typical values [+] feedback
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